Mojo-V: Secret Computation for RISC-V
https://github.com/toddmaustin/mojo-v
#HackerNews #MojoV #SecretComputation #RISC-V #TechInnovation #OpenSource
Chip Butty
and 1 other
boosted
I have predicted for years that the future of computing is going to be #RISC, probably in the form of #ARM, but #Valve releasing the #SteamFrame today is definitely a nod towards my prediction being accurate.
The future of Linux is one is the few things going right this year.
I have predicted for years that the future of computing is going to be #RISC, probably in the form of #ARM, but #Valve releasing the #SteamFrame today is definitely a nod towards my prediction being accurate.
The future of Linux is one is the few things going right this year.
Upbeat Technology's RISC-V MCU Takes Flight with Near-Threshold Computing
#HackerNews #UpbeatTechnology #RISC-V #MCU #NearThresholdComputing #TechNews #Innovation
alcinnz
boosted
Three years ago, I experimented with introducing automated build testing for RISC-V in Linux GPU drivers. Back then, it was a bit hacky due to the older Debian version used in CI [ https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19917 ]
Recently, Mesa3D CI was upgraded to Debian 13, which supports RISC-V out of the box — and we’ve already been testing basic RISC-V builds for the past two days!
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37445
Hopefully, Imagination will start testing on real hardware soon!
Three years ago, I experimented with introducing automated build testing for RISC-V in Linux GPU drivers. Back then, it was a bit hacky due to the older Debian version used in CI [ https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19917 ]
Recently, Mesa3D CI was upgraded to Debian 13, which supports RISC-V out of the box — and we’ve already been testing basic RISC-V builds for the past two days!
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37445
Hopefully, Imagination will start testing on real hardware soon!
RISC-V takes first step toward international ISO/IEC standardization
https://riscv.org/blog/risc-v-jtc1-pas-submitter/
#HackerNews #RISC-V #ISO #standardization #RISC-V #community #technology #innovation #open-source
Easy RISC-V: An interactive introduction to RISC-V assembly programming
https://dramforever.github.io/easyriscv/
#HackerNews #EasyRISC-V #RISC-V #Assembly #Programming #InteractiveLearning #TechEducation #AssemblyLanguage
Did you know that the 'NT' in Windows NT stood for "Nine Ten"?
The intended core platform for the OS was the then-expected Intel i910 RISC processor, which was to be the rebranded moniker for the i860 that can be found in the wild.
It never came to be due to the i860s terrible handling of context switching -- a capability that a CPU for a multitasking, multiuser workstation OS must be able to do very_efficiently. The i860 wasn't.
https://www.youtube.com/watch?v=WTkFGZqVCM8&t=459s
** EDIT: Several have pointed to sources indicating differently that NT stood for N10, which was the codename for the i860, so -- N10, N-Ten > NT.
#TIL#WindowsNT#Windows#Intel #i860 #i910 #vintagecomputing #retrocomputing#OS#techhistory#RISC #x86 #processors #computers #computinghistory#Microsoft
"Have you ever designed your own ISA, built a processor of that ISA on FPGA, and built a compiler for it? Furthermore, have you run an operating system on that processor? Actually, we have."
https://fuel.edby.coffee/posts/how-we-ported-xv6-os-to-a-home-built-cpu-with-a-home-built-c-compiler