Implementation of a Java Processor on a FPGA
https://mavmatrix.uta.edu/electricaleng_theses/337/
#HackerNews #JavaProcessor #FPGA #Implementation #Electronics #Engineering #Technology
#Tag
Implementation of a Java Processor on a FPGA
https://mavmatrix.uta.edu/electricaleng_theses/337/
#HackerNews #JavaProcessor #FPGA #Implementation #Electronics #Engineering #Technology
FPGA Based IBM-PC-XT
https://bit-hack.net/2025/11/10/fpga-based-ibm-pc-xt/
#HackerNews #FPGA #IBM #PC #XT #Retro #Computing #Hardware #Innovation
Interesting SPI Routing with iCE40 FPGAs
https://danielmangum.com/posts/spi-routing-ice40-fpga/
#HackerNews #SPI #Routing #iCE40 #FPGAs #FPGA #Design #Hardware #Development #Tech #Innovation
more digital logic design as handicraft: Texas Instruments, 122 transistor logic chip (c. 1976, experimental)
At the time this plot was hand drafted, it was still possible to verify the design of individual components visually. To repeat a circuit element multiple times, an engineer would trace the initial drawing of the component, photocopy it onto mylar, then cut and glue it onto the diagram. The collage technique is referred to as "paper-doll layout." Intended for use in a military computer, this particular chip was designed to sense low-level memory signals, amplify the signals to a specific size, and then store them in a memory cell for later recall.ref: Information Art: Diagramming Microchips (1990) on moma.org
more digital logic design as handicraft: Texas Instruments, 122 transistor logic chip (c. 1976, experimental)
At the time this plot was hand drafted, it was still possible to verify the design of individual components visually. To repeat a circuit element multiple times, an engineer would trace the initial drawing of the component, photocopy it onto mylar, then cut and glue it onto the diagram. The collage technique is referred to as "paper-doll layout." Intended for use in a military computer, this particular chip was designed to sense low-level memory signals, amplify the signals to a specific size, and then store them in a memory cell for later recall.ref: Information Art: Diagramming Microchips (1990) on moma.org
wireguard-fpga: Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain
wireguard-fpga: Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain
I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
I am happy to announce the FemtoMSP430, a processor designed with the instruction set of the classic #MSP430, but with a flexible bus interface similar to @BrunoLevy01 #FemtoRV32 including memory busy signaling. The playground contains a phantasy "microcontroller" design for the #ULX3S #FPGA board, interactively running the original #Mecrisp #Forth image for MSP430G2755, enhanced with a text mode on 800x600 video, USB-CDC terminal and a lot of GPIO wires: https://codeberg.org/Mecrisp/FemtoMSP430
It's hard to believe, but it's a victory!
The left LEDs are the address, while the SDRAM is being written to, the middle row of LEDs is silent because it is read data, but when the mode switches to read, it comes to life and displays the data read from memory. And the right LEDs are control signals - you know, RAS, CAS, WE.😉
Yes, it's 16 MHz and byte access, but damn it, this thing finally works!🤣
#fpga#apicula#gowin
Keeping track of progress of the Z80 Noveau FPGA-based project. Now with sprites!
Details of the sprite logic in the Z80 Nouveau VDP finite state machine Verilog modules.
This provides an implementation of a TI9118-compatible graphic display.
@ John's Basement
Keeping track of progress of the Z80 Noveau FPGA-based project. Now with sprites!
Details of the sprite logic in the Z80 Nouveau VDP finite state machine Verilog modules.
This provides an implementation of a TI9118-compatible graphic display.
@ John's Basement
The slides of my talk at #orconf2025 about using #guix in the context of #fpga development.
https://gitlab.com/csantosb/ip/talks/guix-fpga
https://mastodon.social/users/fossifoundation/statuses/115191366166341232
The slides of my talk at #orconf2025 about using #guix in the context of #fpga development.
https://gitlab.com/csantosb/ip/talks/guix-fpga
https://mastodon.social/users/fossifoundation/statuses/115191366166341232
Btw, a fun mathematics problem with many practical #FPGA / #DSP applications:
My intuition suggests, they probably exist, but using them may introduce an additional complexity of localised representational slack, and when multiplied repeatedly, they may require occasional re-fluffing to spread the slack around and improve the worst case timing. But I don't yet know in detail what these representations would look like, plus all the ones that I can vaguely see are complicated to convert to and from the conventional integer representation.
AFAIK, there hasn't been a hardware implementation of #uxn thus far.
The instruction set is pretty simple, the core is just 100 lines of C. I'd surmise it could be implemented in the very dinkiest #fpga, and using some kind of TTL asic or something (I'm way, way, way beyond my competency, here (and almost everywhere else, lolol)) should be quite doable.
Of course, stuff like graphics would be more complex, as it gives you any 4 colors out of a range of 4096, and the display size can be variable, but it's been implemented on reasonably limited hardware like the #PlayDate and Gameboy Advance.
I'm kind of wondering if anyone has attempted a true 8-bit implementation, like on a #Commodore64. XD
The cell-based coloring system of most 8-bit micros would be challenging to adapt uxn to, unless you just assumed monochrome.
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