my meat-brain has made some FPGA gateware that's reasonably UART-receiver shaped. Need to write all the tests for it now, including the tests that force it into error conditions
A FPGA UART receiver? Sounds pretty simple, and indeed some of them are. This one isn’t - there's a heap of RX-side analysis happening on the signal to make the receiver tolerant of some amount of noise, to constantly adjust inter-bit timing between every RX bit, and to attempt frame re-alignment on repeated sequential framing errors.
The transmitter side has been tested right down 1 clock per bit, and the receiver works as fast as 4 clocks per bit. Typical low-end FPGAs usually have around a 200MHz PLL inside, so... uh... it should be able to RX at 50MBaud on even a small FPGA? I think that should be fast enough for just about anyone's crazy use-case.
Anyway, if you want an idea of how much faster a FPGA is than a normal CPU for running logic circuits, this simulation has been running for over 3 hours, and has produced about 4 minutes worth of data using a simulated 1MHz clock. On real FPGA hardware I have on hand, I would be using 20MHz to 50MHz clock speed to start with.
Also, the surfer waveform viewer is coping heroically with a now >15GiB .vcd file on this machine with only 16 gigarams!
