my meat-brain has made some FPGA gateware that's reasonably UART-receiver shaped. Need to write all the tests for it now, including the tests that force it into error conditions
A FPGA UART receiver? Sounds pretty simple, and indeed some of them are. This one isn’t - there's a heap of RX-side analysis happening on the signal to make the receiver tolerant of some amount of noise, to constantly adjust inter-bit timing between every RX bit, and to attempt frame re-alignment on repeated sequential framing errors.
The transmitter side has been tested right down 1 clock per bit, and the receiver works as fast as 4 clocks per bit. Typical low-end FPGAs usually have around a 200MHz PLL inside, so... uh... it should be able to RX at 50MBaud on even a small FPGA? I think that should be fast enough for just about anyone's crazy use-case.
