jbz
boosted
#Gentoo #Linux Made Progress On #RISCV, #WSL & More In 2025 While Pulling In Just $12k USD
Gentoo in 2025 moved away from GitHub to the #Forgejo-based #Codeberg in order to avoid Microsoft Copilot usage of their repositories. On the financial front, Gentoo moved their financial structure over to Software in the Public Interface ( #SPI).
https://www.phoronix.com/news/Gentoo-2025-Accomplishments
#Gentoo #Linux Made Progress On #RISCV, #WSL & More In 2025 While Pulling In Just $12k USD
Gentoo in 2025 moved away from GitHub to the #Forgejo-based #Codeberg in order to avoid Microsoft Copilot usage of their repositories. On the financial front, Gentoo moved their financial structure over to Software in the Public Interface ( #SPI).
https://www.phoronix.com/news/Gentoo-2025-Accomplishments
Chip Butty
boosted
"GNU #Guix 1.5 llega con soporte #riscv, GNU Hurd y mas. Fiel a su filosofía, el proyecto ha logrado un avance impresionante en la «cadena de confianza» del software."
https://blog.desdelinux.net/gnu-guix-1-5-0-lanzamiento-hurd-riscv-gnome-46-novedades/
"GNU #Guix 1.5 llega con soporte #riscv, GNU Hurd y mas. Fiel a su filosofía, el proyecto ha logrado un avance impresionante en la «cadena de confianza» del software."
https://blog.desdelinux.net/gnu-guix-1-5-0-lanzamiento-hurd-riscv-gnome-46-novedades/
The Loongson 3A6000 mini-PC offers a glimpse into modern computing on a new, Linux-first RISC architecture. While not particularly fast or power-efficient, it provides usable performance for daily tasks.
Its LoongArch64 ISA, inspired by MIPS and RISC-V, represents an effort toward technological independence.For enthusiasts and developers, it’s an affordable and interesting platform to explore beyond x86_64 and ARM.
SpacemiT K3 is an upcoming 16-core RISC-V processor. Early benchmarks show better-than-RK3588 multi-core performance, even with only half the CPU cores enabled. https://www.cnx-software.com/2026/01/23/spacemit-k3-16-core-risc-v-soc-system-information-and-early-benchmarks/ #SpacemiTK3 #RiscV
der.hans
boosted
A new #DestinationLinux has hit the road! 😂❤️🐧🐧🐧
https://youtu.be/1YoXdfGtPpw
We have an amazing interview, the future of open computing and RISC-V with the CEO of DeepComputing, Yuning Liang! 🎉
A new #DestinationLinux has hit the road! 😂❤️🐧🐧🐧
https://youtu.be/1YoXdfGtPpw
We have an amazing interview, the future of open computing and RISC-V with the CEO of DeepComputing, Yuning Liang! 🎉
Milk-V Titan Mini-IX board with UR-DP1000 processor shows RISC-V ecosystem taking shape — M.2, DDR4, and PCIe card support form a kit that you can use out of the box.
Alex Akselrod
boosted
This Saturday more than 50 kids from the High School of Mathematics OMG "Akademik Kiril Popov" in Plovdiv soldered their first RISC-V Open Source hardware retro like computer RVPC and played TETRIS on it https://olimex.wordpress.com/2026/01/19/risc-v-eur-1-retro-computer-soldering-workshop-at-high-school-of-mathematics-in-plovdiv/ #riscv #retrocomputing #workshop #soldering
3 media
This Saturday more than 50 kids from the High School of Mathematics OMG "Akademik Kiril Popov" in Plovdiv soldered their first RISC-V Open Source hardware retro like computer RVPC and played TETRIS on it https://olimex.wordpress.com/2026/01/19/risc-v-eur-1-retro-computer-soldering-workshop-at-high-school-of-mathematics-in-plovdiv/ #riscv #retrocomputing #workshop #soldering
3 media
Michael Dexter
boosted
I have that page about Arm cpu cores and their features.
RISC-V cpus has insane amount of extensions. I wonder when someone will make similar page about their details.
https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-cpu-cores.html
I have that page about Arm cpu cores and their features.
RISC-V cpus has insane amount of extensions. I wonder when someone will make similar page about their details.
https://gpages.juszkiewicz.com.pl/arm-socs-table/arm-cpu-cores.html
Qualcomm is acquiring RISC-V chip developer Ventana Micro Systems to bulk up its own development of chips based on the RISC-V architecture. https://www.qualcomm.com/news/releases/2025/12/qualcomm-acquires-ventana-micro-systems--deepening-risc-v-cpu-ex #Qualcomm #VentanaMicroSystems #RISCV
An open source online assembler and disassembler for x86, ARM, RISC-V and PowerPC. It's a useful learning resource that comes with other tools and can run offline.
Update: The BPI-CM6 compute module with a SpacemiT K1 RISC-V processor is now available for $67 + shipping (or $84 for a bundle that includes a carrier board). https://liliputing.com/banana-pi-bpi-cm6-is-a-compute-module-with-a-spacemit-k1-risc-v-processor/ #RISCV #SpaceMiTK1 #BananaPi #ComputeModule #BananaPiBPI-CM6
marc0s
boosted
La Catalana OpenChip, tanca acords amb la Japonesa NEC per fabricar xips RISC-V amb extensions vectorials dissenyades per accelerar la IA. https://www.hpcwire.com/2025/11/13/openchip-and-nec-moving-ahead-with-risc-v-vpus-for-aurora/ #riscv
La Catalana OpenChip, tanca acords amb la Japonesa NEC per fabricar xips RISC-V amb extensions vectorials dissenyades per accelerar la IA. https://www.hpcwire.com/2025/11/13/openchip-and-nec-moving-ahead-with-risc-v-vpus-for-aurora/ #riscv
For folks who missed my #KISV keynote or #CHERITech talk, I wanted to pull out the two key points.
The first is that CHERI solves memory safety, but that’s almost incidental. I don’t want to downplay addressing the root cause of 70% of vulnerabilities but that’s not the goal. CHERI was originally designed to support scalable fine-grained compartmentalisation. To do that well, you need a programmer model. You need to be able to share things programmers understand (objects, in object graphs) not pages. And that means you need to be able to trivially map your protection up to language-level constructs like pointers / references and protect both them and the objects that they refer to. And so you need to build memory safety. And, it turns out, making an entire program memory safe is much easier than making just an exposed API memory safe. So we have memory-safe C/C++ and we can use those from languages like Java or Rust to ensure that the C/C++ doesn’t violate the guarantees that the safe language’s security depends on. And then we can use that for easy to use compartmentalisation, safe FFI, supply-chain security, and many more things.
The second is that CHERI is still quite young. I gave a talk about how CHERI impacted OS design. That’s like, in 1985, asking someone from IBM to give a talk about how MMUs impacted OS design. They would tell you you could create VMs to consolidate multiple minicomputers onto a single mainframe. They would tell you that you could enforce process isolation. And, just like the things we can do with CHERI today, these are hugely valuable. But they wouldn’t tell you about using Zygote models to speed up process creation. They wouldn’t tell you about how memory-mapped files could enable new I/O models. They wouldn’t tell you about how IOMMUs could enable kernel-bypass storage and networking. They wouldn’t tell you about how MMUs can introduce lightweight GC barriers. They wouldn’t tell you about how MMUs enable lightweight CoW snapshots for time-trace debugging. Because, although a lot of the hardware existed for these things (and the rest was a fairly small incremental tweak on existing ideas), most of these software uses hadn’t been invented.
CHERI is exactly the same. We have barely scratched the surface of what CHERI can let you build. The BLACKOUT work (presented at CCS and again at CHERITech) is another great example of this. I had never thought of using CHERI as a building block for providing a clean programmer model for avoiding side channels, but some other smart people did and proposed a really interesting model for doing so. I hope future CHERI systems will incorporate something based on this work.
As with MMUs in the early ‘80s, we have no idea what people will be building on top of CHERI in ten or twenty years. Many of these things will be possible on existing implementations, some will require hardware changes. This is why it’s very important for the RISC-V CHERI standard to be designed with agility in mind, so that future hardware can continue to add new and exciting features without breaking backwards compatibility for software. I think we’re on a good path to that.