Our lead relay engineer @alexhaydock has increased our stateless #Tor exit relay deployment to 96! (+1 because of the new #RISCV bare-metal node, +1 other we redeployed due to a silly spelling error). We're stress testing our three AMD Epyc 7402P servers that use #Proxmox.

Each one of the 96 Tor exit nodes are diskless Unified Kernel Images, 56MB in total size, using @alpinelinux's alpine-make-rootfs with an absolutely bare minimum number of packages. We'll be publishing more about our new architecture and configuration soon.

#AlpineLinux #privacy #anonymity#AntiCensorship#AccessToInformation#TorOps#TorOperators

Our lead relay engineer @alexhaydock has increased our stateless #Tor exit relay deployment to 96! (+1 because of the new #RISCV bare-metal node, +1 other we redeployed due to a silly spelling error). We're stress testing our three AMD Epyc 7402P servers that use #Proxmox.

Each one of the 96 Tor exit nodes are diskless Unified Kernel Images, 56MB in total size, using @alpinelinux's alpine-make-rootfs with an absolutely bare minimum number of packages. We'll be publishing more about our new architecture and configuration soon.

#AlpineLinux #privacy #anonymity#AntiCensorship#AccessToInformation#TorOps#TorOperators

🐧Linus Torvalds Rejects RISC-V Changes For Linux 6.17: "Garbage" • Phoronix

｢ Linus Torvalds has used his authority to reject the RISC-V architecture changes for the Linux 6.17 kernel. The RISC-V updates won't land this cycle and will need to try again for v6.18 later in the year ｣

https://www.phoronix.com/news/Linux-6.17-RISC-V-Rejected

#linux #kernel #riscv #opensource

I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. 💛

I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. 💛

A history of MIPS, the processor architecture and the chip making company.

https://thechipletter.substack.com/p/mips

#retrocomputing #mips #riscv

Building Olimex's EUR 1.00 RISC-V Retro Like PC and exploring RISC-V instruction set with WozMon by Benard Mesander https://needlesscomplexity.substack.com/p/building-the-olimex-rvpc-retrocomputer7 #riscv #retrocomputing #assembler

｢ With the Debian 13.0 release planned for 9 August, one of the notable fundamental features with this Debian "Trixie" release is now supporting RISC-V as an official CPU architecture ｣

https://www.phoronix.com/news/Debian-13-RISC-V-Ready

#riscv #debian #opensource

Building Olimex's EUR 1.00 RISC-V Retro Like PC and exploring RISC-V instruction set with WozMon by Benard Mesander https://needlesscomplexity.substack.com/p/building-the-olimex-rvpc-retrocomputer7 #riscv #retrocomputing #assembler

By Anton Shilov for @TomsHardware - #NVIDIA#CUDA now supports #RISCV - is this a signal of broader ecosystem support?

https://www.tomshardware.com/pc-components/gpus/nvidias-cuda-platform-now-supports-risc-v-support-brings-open-source-instruction-set-to-ai-platforms-joining-x86-and-arm

Asm Editor is a web app IDE for learning, developing, and running x86, M68K, RISC-V, and MIPS Assembly code. It features an editor, assembler, and debugger, as well as other tools and learning resources.

https://asm-editor.specy.app

https://github.com/Specy/asm-editor

#x86 #m68k #mips #assembly #riscv

Asm Editor is a web app IDE for learning, developing, and running x86, M68K, RISC-V, and MIPS Assembly code. It features an editor, assembler, and debugger, as well as other tools and learning resources.

https://asm-editor.specy.app

https://github.com/Specy/asm-editor

#x86 #m68k #mips #assembly #riscv

Okay this is super cool to see 😊 https://www.youtube.com/watch?v=HRfbQJ6FdF0

#riscv #cluster

Okay this is super cool to see 😊 https://www.youtube.com/watch?v=HRfbQJ6FdF0

#riscv #cluster