Barebones RISC-V OS written in Zig / Timmy Xiao
🦾 ESWIN Launching EBC7702 Mini-DTX RISC-V Board With Dual-Die EIC7702X SoC - Phoronix
｢ For those looking for a new RISC-V desktop option, ESWIN is launching a EBC7702 mini-DTX board powered by the EIC7702X dual-die SoC. The EBC7702 Mini-DTX is aiming for developers who want RISC-V under their desk for working on AI and other development tasks ｣
Your spooky 'net denizen
boosted
New semester, new version of the xv6 educational OS for RISC-V from MIT! This is accompanied by a new revision 5 of the xv6 book and–for the first time, I think–a Lions' Commentary-style code reader booklet!
A previous version switched to using the stimecmp extension instead of the regular CLINT timer, that was a bit of a surprise. So let's see what the changes in this new version are...
https://pdos.csail.mit.edu/6.1810/2025/xv6/book-riscv-rev5.pdf
https://pdos.csail.mit.edu/6.1810/2025/xv6/xv6-src-booklet-rev5.pdf
https://github.com/mit-pdos/xv6-riscv
New semester, new version of the xv6 educational OS for RISC-V from MIT! This is accompanied by a new revision 5 of the xv6 book and–for the first time, I think–a Lions' Commentary-style code reader booklet!
A previous version switched to using the stimecmp extension instead of the regular CLINT timer, that was a bit of a surprise. So let's see what the changes in this new version are...
https://pdos.csail.mit.edu/6.1810/2025/xv6/book-riscv-rev5.pdf
https://pdos.csail.mit.edu/6.1810/2025/xv6/xv6-src-booklet-rev5.pdf
https://github.com/mit-pdos/xv6-riscv
deutrino
boosted
Our lead relay engineer @alexhaydock has increased our stateless #Tor exit relay deployment to 96! (+1 because of the new #RISCV bare-metal node, +1 other we redeployed due to a silly spelling error). We're stress testing our three AMD Epyc 7402P servers that use #Proxmox.
Each one of the 96 Tor exit nodes are diskless Unified Kernel Images, 56MB in total size, using @alpinelinux's alpine-make-rootfs with an absolutely bare minimum number of packages. We'll be publishing more about our new architecture and configuration soon.
#AlpineLinux #privacy #anonymity#AntiCensorship#AccessToInformation#TorOps#TorOperators
Proxmox host 1 performance snapshot showing 42% CPU usage and 85% RAM usage
Proxmox host 2 performance snapshot showing 8% CPU usage and 85% RAM usage
Proxmox host 3 performance snapshot showing 3% CPU usage and 85% RAM usage
a listing of Emerald Onion's Tor exit relays as displayed on metrics.torproject.org when searching by ASN. "Showing 1 to 10 of 98 entries"
Our lead relay engineer @alexhaydock has increased our stateless #Tor exit relay deployment to 96! (+1 because of the new #RISCV bare-metal node, +1 other we redeployed due to a silly spelling error). We're stress testing our three AMD Epyc 7402P servers that use #Proxmox.
Each one of the 96 Tor exit nodes are diskless Unified Kernel Images, 56MB in total size, using @alpinelinux's alpine-make-rootfs with an absolutely bare minimum number of packages. We'll be publishing more about our new architecture and configuration soon.
#AlpineLinux #privacy #anonymity#AntiCensorship#AccessToInformation#TorOps#TorOperators
Proxmox host 1 performance snapshot showing 42% CPU usage and 85% RAM usage
Proxmox host 2 performance snapshot showing 8% CPU usage and 85% RAM usage
Proxmox host 3 performance snapshot showing 3% CPU usage and 85% RAM usage
a listing of Emerald Onion's Tor exit relays as displayed on metrics.torproject.org when searching by ASN. "Showing 1 to 10 of 98 entries"
🐧Linus Torvalds Rejects RISC-V Changes For Linux 6.17: "Garbage" • Phoronix
｢ Linus Torvalds has used his authority to reject the RISC-V architecture changes for the Linux 6.17 kernel. The RISC-V updates won't land this cycle and will need to try again for v6.18 later in the year ｣
Alex Akselrod
boosted
I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. 💛
I love to hear about interesting accounts to follow for #FPGA, #riscv, #oshw, and #permacomputing. 💛
A history of MIPS, the processor architecture and the chip making company.
vruz
boosted
Building Olimex's EUR 1.00 RISC-V Retro Like PC and exploring RISC-V instruction set with WozMon by Benard Mesander https://needlesscomplexity.substack.com/p/building-the-olimex-rvpc-retrocomputer7 #riscv #retrocomputing #assembler
｢ With the Debian 13.0 release planned for 9 August, one of the notable fundamental features with this Debian "Trixie" release is now supporting RISC-V as an official CPU architecture ｣
Building Olimex's EUR 1.00 RISC-V Retro Like PC and exploring RISC-V instruction set with WozMon by Benard Mesander https://needlesscomplexity.substack.com/p/building-the-olimex-rvpc-retrocomputer7 #riscv #retrocomputing #assembler
By Anton Shilov for @TomsHardware - #NVIDIA#CUDA now supports #RISCV - is this a signal of broader ecosystem support?
Joel 🔪 May-Kill 🔪
boosted
Asm Editor is a web app IDE for learning, developing, and running x86, M68K, RISC-V, and MIPS Assembly code. It features an editor, assembler, and debugger, as well as other tools and learning resources.
Asm Editor is a web app IDE for learning, developing, and running x86, M68K, RISC-V, and MIPS Assembly code. It features an editor, assembler, and debugger, as well as other tools and learning resources.
alcinnz
boosted
Okay this is super cool to see 😊 https://www.youtube.com/watch?v=HRfbQJ6FdF0
Okay this is super cool to see 😊 https://www.youtube.com/watch?v=HRfbQJ6FdF0