Post · bonfire.cafe

sometimes people ask me: “Wanda, why do catgirls bite people”?

I’d like to present two screenshots. the first one is Virtex-4 documentation. I hoped it was a typo. no, the document makes it pretty clear in several other places that they did, in fact, actually do that.

then I looked at the Virtex-5 documentation. it took me several minutes of staring at it to figure out just what the fuck is going on. they have, somehow, managed to make it even worse.

2 media

Virtex-4 documentation screenshot, saying: "Parallel data inputs for SelectMAP modes. For 8-bit SelectMAP: D0 = MSB, D7 = LSB. For 32-bit SelectMAP: D0 = LSB, D31 = MSB."

Screenshot of Virtex-5 documentation, saying:

Traditionally, in SelectMAP x8 mode, configuration data is loaded one byte per CCLK, with the most-significant bit (MSB) of each byte presented to the D0 pin. Although this convention (D0 = MSB, D7 = LSB) differs from many other devices, it is consistent across all Xilinx FPGAs. The bit-swap rule also applies to Virtex-5 BPI-Up and BPI-Down x8 modes (see “Bit Swapping,” page 21).

In Virtex-5 devices, the bit-swap rule is extended to x16 and x32 bus widths. That is, the data is bit swapped within each byte. Virtex-4 SelectMAP x32 mode does not bit swap.

Table 1-7 and Table 1-8 show examples of a sync word inside a bitstream. These examples illustrate what is expected at the FPGA data pins when using parallel configuration modes, such as Slave SelectMAP, Master SelectMAP, BPI-Up, and BPI-Down modes.

Table 1-7: Sync Word Bit Swap Example

Sync word bitstream format: [31:24]¹ 0xAA, [23:16] 0x99, [15:8] 0x55, [7:0] 0x66;
Sync word bit swapped: [31:24]¹ 0x55, [23:16] 0x99, [15:8] 0xaa, [7:0] 0x66

Notes: ¹ [31:24] changes from 0xAA to 0x55 after bit swapping.

Table 1-8: Word Data Sequence Example for x8, x16, and x32 Modes

D[7:0] pins for x8: CCLK cycle 1: 0x55, 2: 0x99, 3: 0xaa, 4: 0x66
[D15:0] pins for x16: CCLK cycle 1: 0x5599, 2: 0xaa66
[D31:0] pins for x32: CCLK cycle 1: 0x5599aa66 — Screenshot of Virtex-5 documentation, saying: Traditionally, in SelectMAP x8 mode, configuration data is loaded one byte per CCLK, with the most-significant bit (MSB) of each byte presented to the D0 pin. Although this convention (D0 = MSB, D7 = LSB) differs from many other devices, it is consistent across all Xilinx FPGAs. The bit-swap rule also applies to Virtex-5 BPI-Up and BPI-Down x8 modes (see “Bit Swapping,” page 21). In Virtex-5 devices, the bit-swap rule is extended to x16 and x32 bus widths. That is, the data is bit swapped within each byte. Virtex-4 SelectMAP x32 mode does not bit swap. Table 1-7 and Table 1-8 show examples of a sync word inside a bitstream. These examples illustrate what is expected at the FPGA data pins when using parallel configuration modes, such as Slave SelectMAP, Master SelectMAP, BPI-Up, and BPI-Down modes. Table 1-7: Sync Word Bit Swap Example Sync word bitstream format: [31:24]¹ 0xAA, [23:16] 0x99, [15:8] 0x55, [7:0] 0x66; Sync word bit swapped: [31:24]¹ 0x55, [23:16] 0x99, [15:8] 0xaa, [7:0] 0x66 Notes: ¹ [31:24] changes from 0xAA to 0x55 after bit swapping. Table 1-8: Word Data Sequence Example for x8, x16, and x32 Modes D[7:0] pins for x8: CCLK cycle 1: 0x55, 2: 0x99, 3: 0xaa, 4: 0x66 [D15:0] pins for x16: CCLK cycle 1: 0x5599, 2: 0xaa66 [D31:0] pins for x32: CCLK cycle 1: 0x5599aa66

Wanda

@mwk@donotsta.re · 2 hours ago

it has been brought to my attention that some people, in fact, get off on catgirl bites. for the sake of all of us, I would like to remind everyone that you can just politely ask a catgirl to bite you, you don’t need to make batshit hardware.