Over the past couple days I broke complex-number arithmetic, & in turn trigonometry, down into floating point multiply-adders. So how'd I design such a multiply-adder?
IEEE 754 suggests encoding real numbers as a 1bit sign, 8bit exponent, & 23bit fraction. With an implicitly preceding "1." on the fraction. IEEE 754 suggests adding 127 offset to the exponent, but it may save circuitry if we instead encode it internally as 2's complement.
Makes multiply easy!
1/3?
To multiply 2 single-precision floating points we XOR the signs, add the exponents, & multiply the fractions adding a leading 1. And if the multiply overflows, increment exponent & shift the fraction.
Except to get more range in this encoding... Don't add that implicit leading 1 on the fraction upon minimum exponent! And to encode errors or infinities... Disable the circuit if the exponent's at its maximum.
As for addition/subtraction... We 1st subtract/compare the exponents.
2/3?
This comparison lets us choose which exponent to keep & which operand gets bitshifted. With the appropriate operands shifted, negated, & implicit leading 1 (if any) implied it adds them.
Upon overflow it increments the exponent & bitshifts the fraction, before checking if the fraction has leading zeroes to bitshift away adjusting the exponent to match. Counting those leading zeroes is a simple combinatorial circuit.
Merging these multiply & add/subtract circuits parallelizes cleanly!
3/3.5!
Finally I'll remark: I've already designed circuitry to handle the underlying integral arithmetic, & have done so recently in the context of my last microcontroller. So I won't revisit it again.
What I will do is look at the FFT pseudocode again, & take another look at how I'd implement it in microcode. Alongside what additional microcode I'd need!
3.5/3.5 Fin for today!
