Post
Finishing my exploration of how I'd (re)design a control unit, not all the opcodes neatly fit within the classifications described yesterday. Some because there's not enough addressing-space (lets ignore this issue as uninteresting), others because they have special needs.
One thing we can do to free up opcode space is to half or quarter how many of the 32 registers can be operands, which yesterday suggested doing for multiplication.
1/4?
It'd certainly be appropriate to half the number of registers available for moving a value between any register pair, which incidentally I needed to repurpose the operand-fetch buses for.
To avoid weird bugs I'd specifically want opcode 0 to be noop.
For the sake of structs it'd be handy to include an offset-fetch opcode. With a read/write bit, a bit for which 16bit register holds the address, 5bit register ID, & 6bit literal offset... Leaves 3bits for the opcode.
2/3?
Control-flow in particular requires special operands!
I'd have a no-operand opcode for jump/call opcode expecting to find the address in certain registers, & possibly an I/O register. Include a couple bits to tweak this opcode's behaviour.
Or I'd have a jump-to-literal with 7 address-bits inline & fetches a further 16 from the next instruction-word, to cover the entire instruction ROM with plenty of room to grow.
Or have a 12bit inline offset with a call/jump opcode.
3/4
For conditional branches we could have 3bits identify to check, 1bit for expected value, & a, say, 7bit offset. Leaves a 5bit opcode.
A couple opcodes could add or subtract a 6bit literal from a value in of 4 register pairs.
A shorthand opcode could read/write a 6bit I/O address. With 5bits for the register, leaves a 5bit opcode. Another address an individual bit in the I/O address & set it to a given value (6bit opcode), whilst similar opcode skip the next if that bit wasn't as expected.
4/5!
To facilitate the skip-next-instruction opcodes (avoiding the need for jump-target operand), & to discard prefetches, this control unit would have a couple latches. One disabling its outputs, the other telling it to also skip the subsequent operand if any.
Then I'd want an opcode for reading/writing any individual in the registers via the T status flag. That's 8 address bits & a read/write flag leaving a 7bit opcode. A similar opcode could skip-next if the bit's the expected value.
5/5!
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