@haitchfive
@haitchfive@oldbytes.space  ·  activity timestamp 3 weeks ago

zen80 update: improved tests

*** Apart from the already substantial unit tests, we now have two additional and rather stringent tests:***

  1. This test loads the ZX Spectrum 128 ROMs (0 and 1) and run that machine's initialisation process. Then it shows a statistical analysis of the instruction coverage that's been executed during rom initialisation. (total percentage of different opcodes executed for each instruction group)

  2. The second big test implements traps as barebones CP/M shims, loads ZEXDOC.COM and runs its extensive stress test (this can be long).

Work is ongoing to support ZEXALL.COM as well, an even more stringent version of zexdoc that also tests undocumented registers and quirks of the Z80, one of the hardest tests known. This will be next, after I'm certain that this passes all ZEXDOC tests without a hitch. So far so good!

#zen80 #emulator#ZXSpectrum#Speccy#Spectrum #golang #foss #z80
@haitchfive
@haitchfive@oldbytes.space replied  ·  activity timestamp 3 weeks ago

Short version: if you pass zexdoc, your core’s documented Z80 instruction semantics are in very good shape.

What a zexdoc PASS does mean

  • ALU ops (8-bit & 16-bit), shifts/rotates, loads/exchanges, block ops (LDI/LDIR/CPIR/…),control flow (JR/JP/CALL/RET) and IX/IY forms behave correctly.
  • The flag results (S, Z, H, P/V, N, C) for those instructions match the spec across lots of edge-case operands.
  • You’re generally safe to run non-weird software that sticks to the documented ISA.

What it doesn’t guarantee

  • Undocumented stuff: opcodes and undocumented flag bits (F3/F5). Use zexall.com for that.
  • Timing: exact T-states per instruction, refresh/M1 cycles, memory contention/waits.
  • Interrupts: IM0/IM1/IM2 behavior, EI/DI one-instruction delay, NMI, HALT wakeup, IFF1/IFF2 edge cases.
  • I/O details: 8- vs 16-bit port masking, IN/OUT block instructions’ exact quirks.
  • R register semantics (incrementing and upper bit behavior).
  • Reset/Power-on register defaults and any bus side effects.