Discussion
I think I have a problem. I'm in the early stages of designing a board, mostly as a challenge but I actually plan to use it.
The design constraints:
* Every IC must be a WLCSP. No other packages allowed regardless of size.
* All passives must be 0201
Initial feasibility study targeting JLC:
* 4 layer
* 0.2mm via pads with 0.1mm through-board drills, no HDI/ELIC/blind/buried.
* 0.1mm trace/space except for 0.075mm allowed in BGA fanout area (which realistically is most of the board area)
The limiting device is probably the STM32L431 which is 0.35mm pitch 8x8 balls. I cannot fit traces between bumps on the outer layers, or between vias if evenly spaced.
@azonenberg oof the cost adder for 0.1mm drills
@jpm cheaper than a "real" fab still though
@azonenberg True. So many cost adders on options you get included with other manufacturers.
I’m also trying their newly-available OSP finish, nice that it's a free option vs leaded HASL
The BGA has four rings of balls in total.
I can fan out the outer ring completely on the front, and the second ring completely on an internal layer.
I can get 7 of 12 of the 3rd ring, leaving 9 unroutable pins, using two signal layers.
Managed to squeeze a bit more on the back layer, plus if I'm allowed to use one of the internal layers for fanout instead of power I can do all but one ball now. This is probably good enough. Nothing here is super fast and I have decoupling caps right next to the die for the power rails.
Plus this is a SoM if I can't stitch all the power rails together easily I can always cheat and make the host board do it for me :p
@azonenberg are internal layers generally reserved for power? Asking as I am just starting to do some PCB layout myself and don't know much about what is best practice! (I'm updating an existing 4-layer OSHW design to change some components).
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