@whitequark @soatok @sophieschmieg

Ibex has a constant-time mode, which makes operations like divide take their worst-case time in all cases. Making divide variable time is more common on simpler pipelines. For out-of-order chips, knowing that each operation takes a fixed number of cycles makes scheduling simpler and, generally, scheduling and register allocation are more power, timing, and area constrained than functional units, so the tradeoff will be between some divides being faster or having more instructions in flight at a time. The latter is usually better.

Specialised ISAs such as OTBN do make constant-time guarantees for divide. Some DSPs do as well.