CPU architecture in which there are no asynchronous interrupts, only hardware tasks that can be suspended waiting for an external event
I also like this but voted no. Cambridge had a research architecture like this and I really liked it when I first saw it: architecturally, you have an unbounded (bounded by memory) set of hyperthreads. Microarchitecturally, you have a finite number and all runnable threads are pulled in when they can be. You can build a system with no register rename or speculation if you do this, which means it can get enormous (GPU-like) aggregate throughput.
The problems come when you want to provide scheduling policies. Think about how you’d implement a priority-inheriting mutex on such a system and you realise quite how complex a hardware-software interface you need. I’m willing to believe it’s possible but it’s a multi-year well-funded prototype to come up with something that actually addresses the hard problems.
