For most use-cases this setup will act like a pure dual-channel setup, considering that most users rarely use all the available memory. It's even better if the memory dedicated to the integrated GPU comes from the lower addresses where it can get the full bandwidth of a dual-channel setup. 3/5
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They treat the area covered by both channels as if it were a symmetric setup, with cachelines alternating between the two channels. Then comes the area of the larger channel which works purely in single-channel mode. https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-desktop/12th-generation-intel-core-processors-datasheet-volume-1-of-2/011/system-memory-controller-organization-mode-ddr4-5-only/ 2/5
For most use-cases this setup will act like a pure dual-channel setup, considering that most users rarely use all the available memory. It's even better if the memory dedicated to the integrated GPU comes from the lower addresses where it can get the full bandwidth of a dual-channel setup. 3/5
I wonder what AMD does. I noticed while testing memory on a laptop with memtest86 that asymmetric setups have less bandwidth than symmetric ones, which suggests that addresses are striped between the channels, contrary to what Intel does. However I couldn't find any data confirming this in their hardware manuals. But I didn't look too hard and it might not even be mentioned. After all memory channel arrangement is generally neither user-controllable nor user-visible. 4/5
As an additional side-note to this thread it's worth noting that early dual-channel setups were ganged. That is the channels weren't independent, a single cacheline was split over the two channels and a single memory operation would read it from both. Unganged designs came later, where each channel could act independently, and it was only then that we could have different cachelines living on different channels and being accessed independently. 5/5
