@resuna @cstross
That is a 233 MHZ G3 PPC with around 250 nm node size, so about 100x larger transistors than the M4 and M5, the first PPC to have an on-chip cache.
Just by clock it’s 15x times slower than a M4/M5 under full power, but it also single core. So effectively that’s easily 100x less speed by aggregated clock over all cores. It also lacks parallel (vector) instructions, so for certain modern workloads the G3 counts as an abacus.
Memory bandwidth is 0.5 GB/s vs. 155 GB/s today, so a 300x slower access in the G3.
So yes, there is innovation that has happened in the last 25 years.
Lower node size means less distance, less capacity in the connections, higher clock, less voltage, less leakage in the transistors, even higher clock possible due to that, and hence more performance.
Plus a transistor budget from 6.35 million in a G3 to 30 billion in a M4/M5: 100x smaller node size gives you 100x100 times more transistors.
All the parts in that large beige box are now in a single chip, and more.